RESPONSABILITATI / BENEFICII:
Candidates should have a strong academic qualification (1st Class or 2.1 Honours Degree, or Post Graduate Degree) in a relevant discipline, eg. Electronic Engineering, Physics, Computer Science, with 2+ years experience in an ASIC/FPGA design verification environment.
We are looking for people who have experience in the verification of complex systems using SystemVerilog, VMM/OVM or a similar verification language and methodology. Fluency in English is essential.
Candidates should have experience in some of the following areas:
Verification Languages and techniques, SystemVerilog, VMM, OVM.
Assertions, Constrained Random Testing, Test Coverage.
Programming Languages (C++, Java, OOD techniques).
Verilog/VHDL implementation and verification, simulation tools.
SOC Verification. Hardware/Software co-verification
In additional knowledge and experience in the following areas would be beneficial:
Computer Networks, Communications, Multimedia, Automotive Electronics.
Embedded Software Development.
System Design Techniques. SOC. Complex Digital Logic Design. Embedded Sysem Development.
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